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author3gg <3gg@shellblade.net>2025-02-08 18:14:45 -0800
committer3gg <3gg@shellblade.net>2025-02-08 18:14:45 -0800
commit2dd1239ae661a1704c94501bbfc46afd4ca94863 (patch)
treeed441f19b2835807db9ed461f7d1b3db0aa024dc /src/mmio.c
parent9bbddb13df34587d1e664b5f17d50778f6b48f7e (diff)
Comment.HEADmain
Diffstat (limited to 'src/mmio.c')
-rw-r--r--src/mmio.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mmio.c b/src/mmio.c
index 47ef354..e082d66 100644
--- a/src/mmio.c
+++ b/src/mmio.c
@@ -1,5 +1,12 @@
1/*
2References:
3 https://wiki.osdev.org/Raspberry_Pi_Bare_Bones
4 https://jsandler18.github.io/extra/peripheral.html
5 https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
6*/
1#include <mmio.h> 7#include <mmio.h>
2 8
9// Peripheral base address.
3static void* MMIO_BASE; 10static void* MMIO_BASE;
4 11
5void mmio_init(int raspi) { 12void mmio_init(int raspi) {
@@ -11,6 +18,8 @@ void mmio_init(int raspi) {
11 } 18 }
12} 19}
13 20
21// All MMIO registers are 32-bit.
22
14#define REG_ADDR(reg) ((volatile uint32_t*)(MMIO_BASE + reg)) 23#define REG_ADDR(reg) ((volatile uint32_t*)(MMIO_BASE + reg))
15 24
16uint32_t mmio_read(uint32_t reg) { 25uint32_t mmio_read(uint32_t reg) {